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description the a1150, a1152, a1153, a1155, a1156, a1157, and a1158 comprise a family of two-wire, unipolar, hall-effect switches, which are factory-trimmed to optimize magnetic switchpoint accuracy. these devices are produced on the allegro? advanced bicmos wafer fabrication process, which implements a patented high frequency, 4-phase, chopper-stabilization technique. this technique achieves magnetic stability over the full operating temperature range, and eliminates offsets inherent in devices with a single hall element that are exposed to harsh application environments. the a115x family has a number of automotive applications. these include sensing seat track position, seat belt buckle presence, hood/trunk latching, and shift selector position. two-wire unipolar switches are particularly advantageous in cost-sensitive applications because they require one less wire for operation versus the more traditional open-collector output switches. additionally, the system designer inherently gains diagnostics because there is always output current flowing, which should be in either of two narrow ranges. any current level not within these ranges indicates a fault condition. a1152-ds, rev. 5 features and benefits ? high speed, 4-phase chopper stabilization ? low switchpoint drift throughout temperature range ? low sensitivity to thermal and mechanical stresses ? on-chip protection ? supply transient protection ? reverse battery protection ? on-board voltage regulator ? 3.0 to 24 v operation ? solid-state reliability ? robust emc and esd performance ? industry leading iso 7637-2 performance through use of proprietary, 40-v clamping structures chopper-stabilized, two wire hall-effect switches continued on the next page? functional block diagram a1150, a1152, a1153, a1155, a1156, a1157, and a1158 packages approximate footprint 3-pin sot23-w 2 mm 3 mm 1 mm (suffix lh) 3-pin ultramini sip 1.5 mm 4 mm 3 mm (suffix ua) amp regula to all subcircuits tor schmitt trigger polarity low-pass filter gnd vcc gnd ua package only 0.01 f v+ clock/logic dynamic offset cancellation sample and hold
chopper-stabilized, two wire hall-effect switches a1150, a1152, a1153, a1155, a1156, a1157, and a1158 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com nc 1 2 3 1 3 2 all family members are offered in two package styles. the lh is a sot-23w style, miniature, low profile package for surface-mount applications. the ua is a 3-pin, ultra-mini, single inline package (sip) for through-hole mounting. both packages are lead (pb) free, with 100% matte tin leadframe plating. description (continued) absolute maximum ratings characteristic symbol notes rating unit forward supply voltage v cc 28 v reverse supply voltage v rcc ?18 v magnetic flux density b unlimited g operating ambient temperature t a range l ?40 to 150 oc maximum junction temperature t j (max) 165 oc storage temperature t stg ?65 to 170 oc selection guide part number packing 1 package output (i cc ) in south polarity field supply current at i cc(l) (ma) magnetic operate point, b op (g) a1150llhlx-t 13-in. reel, 10 000 pieces/reel 3-pin sot23w surface mount low 2 to 5 50 to 110 a1150lua-t 2 bulk, 500 pieces/bag 3-pin sip through hole a1152llhlx-t 13-in. reel, 10 000 pieces/reel 3-pin sot23w surface mount low 5 to 6.9 a1152lua-t 2 bulk, 500 pieces/bag 3-pin sip through hole a1153llhlx-t 13-in. reel, 10 000 pieces/reel 3-pin sot23w surface mount high a1153lua-t 2 bulk, 500 pieces/bag 3-pin sip through hole a1155llhlx-t 13-in. reel, 10 000 pieces/reel 3-pin sot23w surface mount low 5 to 6.9 20 to 60 a1155lua-t 2 bulk, 500 pieces/bag 3-pin sip through hole a1156llhlx-t 13-in. reel, 10 000 pieces/reel 3-pin sot23w surface mount high a1156lua-t 2 bulk, 500 pieces/bag 3-pin sip through hole a1157llhlx-t 13-in. reel, 10 000 pieces/reel 3-pin sot23w surface mount low 2 to 5 20 to 80 a1157llhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount a1157lua-t 2 bulk, 500 pieces/bag 3-pin sip through hole a1158llhlx-t 13-in. reel, 10 000 pieces/reel 3-pin sot23w surface mount high a1158llhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount a1158lua-t 2 bulk, 500 pieces/bag 3-pin sip through hole 1 contact allegro ? for additional packing options. 2 contact factory for availability. pin-out diagrams lh package ua package terminal list table number name function lh package ua package 1 vcc vcc input power supply 2 nc gnd lh package: no connection ua package: ground terminal 3 gnd gnd ground terminal
electrical characteristics valid at t a = ?40c to 150c, t j < t j (max), c byp = 0.01 f, through operating supply voltage range; unless otherwise noted characteristics symbol test conditions min. typ. max. unit supply voltage 1,2 v cc operating, t j 165 c 3.0 ? 24 v supply current i cc(l) a1150, a1157 b > b op 2.0 ? 5.0 ma a1158 b < b rp a1152, a1155 b > b op 5 ? 6.9 ma a1153, a1156 b < b rp i cc(h) a1150, a1152, a1155, a1157 b < b rp 12 ? 17 ma a1153, a1156, a1158 b > b op supply zener clamp voltage v z(sup) i cc(l) (max) + 3 ma, t a = 25c 28 ? ? v supply zener clamp current i z(sup) v z(sup) = 28 v ? ? i cc(l) (max) + 3 ma ma reverse supply current i rcc v rcc = ?18 v ? ? ?1.6 ma output slew rate 3 di/dt no bypass capacitor, capacitance of probe c s = 20 pf ?90?ma / s chopping frequency f c ? 700 ? khz power-up time 4,5 t on a1150, a1152, a1155, a1157 b > b op + 10 g ??25 s a1153, a1156, a1158 b < b rp ? 10 g power-up state 2,4,6,7 pos t on < t on (max) , v cc slew rate > 25 mv / s?i cc(h) ?? 1 v cc represents the generated voltage between the vcc pin and the gnd pin. 2 the v cc slew rate must exceed 600 mv/ms from 0 to 3 v. a slower slew rate through this range can affect device performance. 3 measured without bypass capacitor between vcc and gnd. use of a bypass capacitor results in slower current change. 4 power-up time is measured without and with bypass capacitor of 0.01 f. adding a larger bypass capacitor would cause longer power-up time. 5 guaranteed by characterization and design. 6 power-up state as defined is true only with a v cc slew rate of 25 mv / s or greater. 7 for t > t on and b rp < b < b op , power-up state is not defined. magnetic characteristics 1 valid at t a = ?40c to 150c, t j < t j (max); unless otherwise noted characteristics symbol test conditions min. typ. max. unit 2 magnetic operating point b op a1150, a1152, a1153 50 ? 110 g a1155, a1156 20 ? 60 g a1157, a1158 20 ? 80 g magnetic release point b rp a1150, a1152, a1153 45 ? 105 g a1155, a1156 10 ? 55 g a1157, a1158 10 ? 60 g hysteresis b hys 5 ? 30 g 1 relative values of b use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore greater b values indicate a stronger south polarity field (or a weaker north polarity field, if pr esent). 2 1 g (gauss) = 0.1 mt (millitesla). chopper-stabilized, two wire hall-effect switches a1150, a1152, a1153, a1155, a1156, a1157, and a1158 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 7 8 9 2 3 4 5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 20 40 60 80 100 120 140 160 180 temperature (oc) maximum allowable v cc (v) power derating curve (r ja = 228 oc/w) 1-layer pcb, package lh (r ja = 110 oc/w) 2-layer pcb, package lh (r ja = 165 oc/w) 1-layer pcb, package ua v cc(min) v cc(max) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (m w) power dissipation versus ambient temperature (r ja = 165 o c/w) 1-lay er pc b, packa ge ua (r ja = 228 oc /w ) 1-lay er pcb, pa ckage l h (r j a = 110 oc/ w) 2-l a yer pcb, packag e lh thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja package lh, on 1-layer pcb with copper limited to solder pads 228 oc/w package lh, on 2-layer pcb with 0.463 in. 2 of copper area each side 110 oc/w package ua, on 1-layer pcb with copper limited to solder pads 165 oc/w *additional thermal information available on the allegro website chopper-stabilized, two wire hall-effect switches a1150, a1152, a1153, a1155, a1156, a1157, and a1158 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
characteristic performance supply voltage, v cc (v) supply current, i cc(h) (ma) 17 16 15 14 13 12 2 6 10 14 18 22 26 t a = 150c t a = ?40c t a = 25c average supply current (high) versus supply voltage a1150/a1152/a1153/a1155/a1156/a1157/a1158 v cc = 3.0 v v cc = 24 v -60 -40 -20 0 20 40 60 80 100 140 120 160 ambient temperature, t a (c) supply current, i cc(h) (ma) 17 16 15 14 13 12 average supply current (high) versus temperature a1150/a1152/a1153/a1155/a1156/a1157/a1158 5.0 4.5 4.0 3.5 3.0 2.5 2.0 supply current, i cc(l) (ma) supply voltage, v cc (v) 2 6 10 14 18 22 26 t a = 150c t a = ?40c t a = 25c 5.0 4.5 4.0 3.5 3.0 2.5 2.0 average supply current (low) versus supply voltage a1150/a1157/a1158 5.0 4.5 4.0 3.5 3.0 2.5 2.0 ambient temperature, t a (c) supply current, i cc(l) (ma) -60 -40 -20 0 20 40 60 80 100 140 120 160 v cc = 3.0 v v cc = 24 v 5.0 4.5 4.0 3.5 3.0 2.5 2.0 ambient temperature, t a (c) -60 -40 -20 0 20 40 60 80 100 140 120 160 v cc = 3.0 v v cc = 24 v average supply current (low) versus temperature a1150/a1157/a1158 t a = 150c t a = ?40c t a = 25c 7.0 6.5 6.0 5.5 5.0 2 6 10 14 18 22 26 supply voltage, v cc (v) supply current, i cc(l) (ma) average supply current (low) versus supply voltage a1152/a1153/a1155/a1156 v cc = 3.0 v v cc = 24 v 7.0 6.5 6.0 5.5 5.0 -60 -40 -20 0 20 40 60 80 100 140 120 160 ambient temperature, t a (c) supply current, i cc(l) (ma) average supply current (low) versus temperature a1152/a1153/a1155/a1156 chopper-stabilized, two wire hall-effect switches a1150, a1152, a1153, a1155, a1156, a1157, and a1158 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
ambient temperature, t a (c) 30 25 20 15 10 5 ambient temperature, t a (c) applied flux density at switchpoint hysteresis, b hys (g) -60 -40 -20 0 20 40 60 80 100 140 120 160 v cc = 3.0 v v cc = 24 v average switchpoint hysteresis versus temperature a1150/a1152/a1153/a1155/a1156/a1157/a1158 v cc = 3.0 v v cc = 24 v ambient temperature, t a (c) -60 -40 -20 0 20 40 60 80 100 140 120 160 30 25 20 15 10 5 applied flux density at switchpoint hysteresis, b hys (g) ambient temperature, t a (c) -60 -40 -20 0 20 40 60 80 100 140 120 160 average switchpoint hysteresis versus temperature a1150/a1152/a1153/a1155/a1156/a1157/a1158 v cc = 3.0 v v cc = 24 v -60 -40 -20 0 20 40 60 80 100 140 120 160 ambient temperature, t a (c) applied flux density at release point, b rp (g) 55 50 45 40 35 30 25 20 15 10 average release point versus temperature a1155/a1156 v cc = 3.0 v v cc = 24 v -60 -40 -20 0 20 40 60 80 100 140 120 160 ambient temperature, t a (c) applied flux density at release point, b rp (g) 105 95 85 75 65 55 45 average release point versus temperature a1150/a1152/a1153 v cc = 3.0 v v cc = 24 v 60 55 50 45 40 35 30 25 20 -60 -40 -20 0 20 40 60 80 100 140 120 160 ambient temperature, t a (c) applied flux density at operate point, b op (g) average operate point versus temperature a1155/a1156 v cc = 3.0 v v cc = 24 v 110 100 90 80 70 60 50 -60 -40 -20 0 20 40 60 80 100 140 120 160 ambient temperature, t a (c) applied flux density at operate point, b op (g) average operate point versus temperature a1150/a1152/a1153 chopper-stabilized, two wire hall-effect switches a1150, a1152, a1153, a1155, a1156, a1157, and a1158 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
functional description b op b rp b hys i cc(h) i cc i cc(l) switch to low switch to high b+ b? i+ 0 (a) hysteresis curve for a1150, a1152, a1155, and a1157 b op b rp b hys i cc(h) i cc i cc(l) switch to high switch to low b+ i+ b? 0 (b) hysteresis curve for a1153, a1156, and a1158 the a1150, a1152, a1155, and a1157 output, i cc , switches low after the magnetic field at the hall sensor ic exceeds the oper- ate point threshold, b op . when the magnetic field is reduced to below the release point threshold, b rp , the device output goes high. this is shown in figure 1, panel a. in the case of the reverse output polarity, as in the a1153, a1156, and a1158, the device output switches high after the magnetic field at the hall sensor ic exceeds the operate point threshold, b op . when the magnetic field is reduced to below the release point threshold, b rp , the device output goes low (panel b). the difference between the magnetic operate and release points is called the hysteresis of the device, b hys . this built-in hyster- esis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. figure 1. alternative switching behaviors are available in the a115x device family. on the horizontal axis, the b+ direction in dicates increasing south polarity magnetic field strength, and the b? direction indicates decreasing south polarity field strength (inc luding the case of increasing north polarity). chopper-stabilized, two wire hall-effect switches a1150, a1152, a1153, a1155, a1156, a1157, and a1158 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
gnd a115x vcc v+ 0.01 f a gnd ecu package ua only a r sense c byp gnd a115x vcc v+ 0.01 f a gnd r sense c byp figure 2. typical application circuits (a) low side sensing (b) high side sensing amp regulator clock/logic hall element sample and hold low-pass filter chopper stabilization technique when using hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the hall element. this voltage is disproportionally small relative to the offset that can be produced at the output of the hall sensor ic. this makes it difficult to process the signal while maintaining an accurate, reliable output over the specified oper- ating temperature and voltage ranges. chopper stabilization is a unique approach used to minimize hall offset on the chip. the patented allegro technique, namely dynamic quadrature offset cancellation, removes key sources of the output drift induced by thermal and mechanical stresses. this offset reduction technique is based on a signal modulation-demodulation process. the undesired offset signal is separated from the magnetic field- induced signal in the frequency domain, through modulation. the subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the dc offset becomes a high-frequency signal. the magnetic-sourced signal then can pass through a low-pass filter, while the modulated dc offset is suppressed. the chopper stabilization technique uses a 350 khz high frequency clock. for demodulation process, a sample and hold technique is used, where the sampling is performed at twice the chopper frequency. this high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. this approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent hall out- put voltages and precise recoverability after temperature cycling. this technique is made possible through the use of a bicmos process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample- and-hold circuits. figure 3. chopper stabilization circuit (dynamic quadrature offset cancellation) chopper-stabilized, two wire hall-effect switches a1150, a1152, a1153, a1155, a1156, a1157, and a1158 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
chopper-stabilized, two wire hall-effect switches a1150, a1152, a1153, a1155, a1156, a1157, and a1158 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the device must be operated below the maximum junction tem- perature of the device, t j (max). under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the appli- cation. this section presents a procedure for correlating factors affecting operating t j . (thermal data is also available on the allegro microsystems web site.) the package thermal resistance, r ? ja , is a figure of merit sum- marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. its primary component is the effective thermal conductivity, k, of the printed circuit board, including adjacent devices and traces. radiation from the die through the device case, r ? jc , is relatively small component of r ? ja . ambient air temperature, t a , and air motion are significant external factors, damped by overmolding. the effect of varying power levels (power dissipation, p d ), can be estimated. the following formulas represent the fundamental relationships used to estimate t j , at p d . p d = v in i in (1) ? ???????????????????????? t = p d r ? ja (2) t j = t a + t (3) for example, given common conditions such as: t a = 25c, v cc = 12 v, i cc = 4 ma, and r ? ja = 140 c/w, then: p d = v cc i cc = 12 v 4 ma = 48 mw ?? t = p d r ? ja = 48 mw 140 c/w = 7c t j = t a + ? t = 25c + 7c = 32c a worst-case estimate, p d (max), represents the maximum allow- able power level (v cc (max), i cc (max)), without exceeding t j (max), at a selected r ? ja and t a . example : reliability for v cc at t a = 150c, package ua, using a low-k pcb. observe the worst-case ratings for the device, specifically: r ? ja = 165 c/w, t j (max) = 165c, v cc (max) = 24 v, and i cc (max) = 17 ma. calculate the maximum allowable power level, p d (max). first, invert equation 3: ? t max = t j (max) ? t a = 165 c ? 150 c = 15 c this provides the allowable increase to t j resulting from internal power dissipation. then, invert equation 2: ???? p d (max) = ? t max r ? ja = 15c 165 c/w = 91 mw finally, invert equation 1 with respect to voltage: v cc(est) = p d (max) i cc (max) = 91 mw 17 ma = 5 v the result indicates that, at t a , the application and device can dissipate adequate amounts of heat at voltages v cc(est) . compare v cc(est) to v cc (max). if v cc(est) v cc (max), then reli- able operation between v cc(est) and v cc (max) requires enhanced r ? ja . if v cc(est) v cc (max), then operation between v cc(est) and v cc (max) is reliable under these conditions. power derating
chopper-stabilized, two wire hall-effect switches a1150, a1152, a1153, a1155, a1156, a1157, and a1158 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lh, 3-pin sot23w 0.55 ref gauge plane seating plane 0.25 bsc 0.95 bsc 0.95 1.00 0.70 2.40 2 1 a active area depth, 0.28 mm ref b c c b reference land pattern layout all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances branding scale and appearance at supplier discretion a pcb layout reference view standard branding reference view 1 branded face n = last two digits of device part number t = temperature code nnt 2.90 +0.10 ?0.20 44 8x 10 ref 0.180 +0.020 ?0.053 0.05 +0.10 ?0.05 0.25 min 1.91 +0.19 ?0.06 2.98 +0.12 ?0.08 1.00 0.13 0.40 0.10 for reference only; not for tooling use (reference dwg-2840) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown d hall element, not to scale d d d 1.49 0.96 3
chopper-stabilized, two wire hall-effect switches a1150, a1152, a1153, a1155, a1156, a1157, and a1158 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ua, 3-pin sip 23 1 1.27 nom 1.02 max 45 45 c 1.52 0.05 b gate and tie bar burr area a b c dambar removal protrusion (6x) a d e d e e 1.44 nom 2.05 nom e active area depth, 0.50 mm ref branding scale and appearance at supplier discretion hall element (not to scale) for reference only; not for tooling use (reference dwg-9065) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown standard branding reference view nnn 1 mold ejector pin indent = supplier emblem n = last three digits of device part number 0.41 +0.03 ?0.06 0.43 +0.05 ?0.07 14.99 0.25 4.09 +0.08 ?0.05 3.02 +0.08 ?0.05 0.79 ref 10 branded face
revision history revision revision date description of revision rev. 5 march 22, 2012 update product selection chopper-stabilized, two wire hall-effect switches a1150, a1152, a1153, a1155, a1156, a1157, and a1158 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for the latest version of this document, visit our website: www.allegromicro.com copyright ?2009-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.

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